1. Field of the Invention
Example embodiments of the present invention relate generally to a memory module, a memory system including a memory controller and a memory module and methods thereof, and more particularly to a memory module, a memory system including a memory controller and a memory module and methods of performing write and read operations.
2. Description of the Related Art
A conventional memory system may include a memory controller and a memory module. The memory module may receive packet commands and may include a plurality of memories. Each of the plurality of memories may receive a packet command having a command, an address, and write data to perform a write operation, and may receive a packet command having a command and an address to perform a read operation.
FIG. 1 is a block diagram illustrating a configuration of a conventional memory system. Referring to FIG. 1, the memory system may include a memory controller 10 and a memory module 20. The memory module 20 may include n memory units MG1 to MGn, and each of the memory units MG1 to MGn may include a first memory M1 and a second memory M2. The first memory M1 of each of the memory units MG1 to MGn may include a repeater R1, and the second memory of each of the memory units MG1 to MGn may include a repeater R2.
Referring to FIG. 1, c/a/wd1 and c/a/wd2 may denote control signal lines, and rd1 and rd2 may denote read data lines.
A data transmission process performed within the conventional memory system shown of FIG. 1 will now be described in greater detail.
Referring to FIG. 1, the memory controller 10 may apply packet commands to the memory module 20 through the control signal lines c/a/wd1, the first memory M1 may receive the packet command and may transfer the packet command to the second memory M2 through the repeater R1 and the control signal lines c/a/wd2.
Referring to FIG. 1, the first memory M1 may analyze the packet command. If the packet command is a write command to the first memory M1, the first memory M1 may store write data contained in the packet command, and if the packet command is a read command from the first memory M1, the first memory M1 may analyze the packet command and may perform a read operation to transmit read data to the read data lines rd1.
Referring to FIG. 1, the second memory M2 may analyze the packet command applied through the control signal lines c/a/wd2. If the packet command is a write command to the second memory M2, the second memory M2 may store write data contained in the packet command, if the packet command is a read command from the first memory M1, the second memory M2 may transmit read data applied through the read data lines rd1 to the read data lines rd2 through the repeater R2; and if the packet command is a read command from the second memory M2, the second memory M2 may perform a read operation to transmit read data through the read data lines rd2.
Referring to FIG. 1, each of the first and second memories M1 and M2 of the memory system shown in FIG. 1 may include both a repeater and a packet command decoder (not shown) for analyzing the packet command. In addition, the first and second memories M1 and M2 of the memory system shown in FIG. 1 may be directly connected to the memory controller 10 to perform operations, such that operating speeds of the first and second memories M1 and M2 may generally increase as a frequency of a system clock signal increases, which in turn may cause each of the first and second memories M1 and M2 of the memory system shown in FIG. 1 to have an additional configuration for interfacing with the memory controller 10.
FIG. 2 is a block diagram illustrating another configuration of a conventional memory system. Referring to FIG. 2, the memory system may include a memory controller 10 and a memory module 20′. The memory module 20′ may include a buffer 20-1 and n memories M1 to Mn. n/2 memories M1 to M(n/2) may be disposed at a first side of the buffer 20-1, and the remainder of the n/2 memories M(n/2+1) to Mn may be disposed at a second side of the buffer 20-1.
Referring to FIG. 2, c/a/wd1 may denote control signal lines, rd may denote read data lines, c may denote command signal lines, a may denote address signal lines, and w/r1 to w/rn may denote write/read data lines.
Referring to FIG. 2, the memory controller 10 may apply a packet command having a command, write data, and an address, or alternatively a packet command having a command and an address, through the control signal lines c/a/wd1. The memory controller 10 may receive read data through the control signal lines rd. The buffer 20-1 may receive and decode the packet command to transmit the command, the address, and the write data to each of the memories M1 to Mn, and may receive the read data transmitted from each of the memories M1 to Mn for transfer to the memory controller 10. If the buffer 20-1 transceives the write/read data with each of the memories M1 to Mn, the buffer 20-1 may transceive data with a given time difference so as to reduce data skews from occurring due to lengths of the write/read data lines w/r1 to w/rn. Also, the buffer 20-1 may process and then transmit and receive a signal so as to comply with a signal transmission speed if the signal transmission speed between the memory controller 10 and the buffer 20-1 is different from that between the memories M1 to Mn and the buffer 20-1.
Accordingly, in the conventional memory module shown in FIG. 2, a given buffer 20-1 may be configured to perform interfacing between the memory controller 10 and the each of the n memories M1 to Mn, which may increase the complexity of the given buffer 20-1, which may likewise increase the complexity of the conventional memory system of FIG. 2.